A solid state drive (SSD) is a data storage device that uses integrated circuit assemblies as memory to store data persistently. SSDs have no moving mechanical components and this distinguishes SSDs from traditional electromechanical magnetic disks, such as, hard disk drives (HDDs) or floppy disks, which contain spinning disks and movable read/write heads. Compared to electromechanical disks, SSDs are typically more resistant to physical shock, run silently, have lower access time, and have less latency. Many types of SSDs use NAND-based flash memory which comprises an electronic (solid-state) non-volatile computer storage medium that can be electrically erased and reprogrammed.
NAND-based flash memory may have bit errors in stored data. To allow recovery from such bit errors, data may be stored in an encoded form in NAND-based flash memory, by using an error correction code (ECC) to encode the data. Error correction techniques may be employed on the encoded data to remove the errors and reconstruct the original data.
Other error correction schemes search for improved read reference voltages in response to read errors. Read failures may originate from numerous error mechanisms and different usage models. These error mechanisms and usage models may alter memory cell threshold voltage (Vt) distributions. Thus, to improve read results, read reference voltage values may be moved to other values at which the reading of the memory cells is retried. This movement of the read reference is referred to as Moving Read Reference (MRR).
MRR schemes can involve numerous attempts to move a read reference before an Error Correction Code (ECC) correctable read reference is found. Large numbers of read retries can result in undesirable high levels of read latency. In order to prevent a large number of re-reads, one approach is to use an MRR table having a fixed number of entries implemented in a fixed order or sequence. However, such fixed MRR tables may not include the optimal set of values or sequence orders due to varying sources of error and different usage conditions.
Another approach is to adapt the values or sequence orders of the MRR table based upon the correction capabilities of various candidate values or sequence orders. As certain values or sequences result in greater rates of read success, the MRR table entries may converge on more optimal settings. However, such adaptations can nonetheless permit high levels of read latency and therefore poor quality of service until the more optimal values or sequence orders are found. Moreover, rates of success may not be sufficient to permit convergence of MRR table entries to values which sufficiently reduce read latency or sufficiently improve quality of service.
If use of such MRR tables to move the read references does not result in ECC correctable read references, other error recovery schemes may be implemented. Also, the memory cell may be deemed as unreadable should the various error recovery schemes all fail.